Important Dates

• Paper submission deadline: June 30, 2026 (all deadlines are 23:59 / 11:59pm AoE)
• Acceptance notification: September 4, 2026
• Camera-ready deadline: September 17, 2026

Overview

Cryptographic implementations that protect critical assets, such as payment systems and secure communications, are subject to strict certification requirements across many industry sectors. However, security against physical attacks, such as side-channel and fault attacks, remains a fundamental challenge. Despite the strong theoretical foundations of masking, real-world implementations frequently fail to meet their expected security levels. This gap arises from mismatches between abstract security models and the physical realities of hardware, including microarchitectural effects. As a result, secure implementations must be carefully tailored to specific platforms, requiring deep expertise in both cryptography and hardware behavior. Formal methods offer mathematical guarantees under simplified assumptions, while practical evaluation captures real-world leakage but provides only partial assurance. ACTIVE welcomes contributions in this area that address aspects of formal verification, practical evaluation, or the gap between them.

Topics of Interest

ACTIVE welcomes submissions on any aspects of technologies that can be used for the verification of cryptographic implementations. Topics of interest include, but are not limited to:

• Automated tools for side-channel and fault analysis
• Formal and empirical verification of cryptographic implementations
• Scalable methods for verifying masked and fault-resistant designs
• Composability and security of cryptographic gadgets
• Side-channel evaluation and countermeasures
• Fault injection and countermeasures
• Bridging formal models and practical evaluation methodologies
• Microarchitectural leakage and its impact on security models
• Hardware/software co-design for secure implementations
• Case studies of certified or evaluated cryptographic systems
• Benchmarking, metrics, and reproducibility in implementation security
• AI/ML-assisted techniques for vulnerability detection and verification
• Integration of formal and empirical evaluation workflows

Submission Guidelines

• Full papers: up to 10 pages in ACM double-column format (including references and appendices);
• Short papers: up to 6 pages in ACM double-column format (including references and appendices);
• Wild and crazy (WaC) papers: 3-6 pages in ACM double-column format (excluding references and appendices); WaC papers target groundbreaking new methods and paradigms for hardware security, emphasizing novelty, potential impact, and plausibility (a full demonstration is not required).

Submission Format

Submitted papers must be written in English and be anonymous, with no author names, affiliations, acknowledgments, or any identifying citations. Papers should begin with a title, a short abstract, and a list of keywords.

Author instructions for paper submission are on the CCS submissions page: https://www.sigsac.org/ccs/CCS2026/

Submission Link